In general, cache memories are arranged as a plurality of "lines", each containing a plurality of "entries" which share a common "tag address", and a corresponding number of "valid" bits which when set indicate the validity of the respective entries in the particular cache line. In normal operation, required operands are requested from a conventional system memory by an appropriate system bus master. If a requested operand is present in the cache memory, the cache provides that operand and the system memory request is aborted. If the requested operand is not in the cache, the operand will be provided by the system memory. Simultaneously, the operand will be stored in the cache, so long as the operand is sufficient to fill a full entry. Typically, the bus master then fetches the other operands having the same tag address in the system memory, to fill the entire cache line. However, if an operand (or some portion of an operand) is fetched that is insufficient in either size or alignment to fill an entire entry, the operand is not cached at all, and the bus master makes no further attempts to fill the other entries in the same cache line.